Verilog Code For 8:3 Encoder | Verilog Example Codes

Encoder is a circuit which converts a larger data-word into smaller data-word by encoding the information in some pattern. The 8:3 encoder takes a word of 8 bits at input and encodes to present a 3 bit word at output. Presented below is a verilog module code for implementation of 8:3 encoder. The code uses verilog case statement.

module encoder (coded, data);

input [7:0] data;

output [2:0] coded;

reg [2:0] coded;

always @ (data)

 begin

  case (data)

8'b00000001 : coded= 0;

8'b00000010 : coded= 1;

8'b00000100 : coded= 2;

8'b00001000 : coded= 3;

8'b00010000 : coded= 4;

8'b00100000 : coded= 5;

8'b01000000 : coded= 6;

8'b10000000 : coded= 7;

  default   : coded= 3'bx;

 endcase

endmodule

If you observe closely then you will see that all the cases which are not presented otherwise are covered by default statement.