D flip flop is a flip flop of simplest type. At every active edge of clock, the value present at the D input port is stored, independent of present stored value. Here is a verilog behavioral model of D flip flop.
module D_flip_flop (Q_out, D_in, reset, clock);
input D_in, reset, clock;
always @ (posedge clock or posedge reset)
if (reset) Q_out <= 1'b0; else
Q_out <= D_in;