Verilog Code For D Flip Flop | Verilog Example Codes

D flip flop is a flip flop of simplest type. At every active edge of clock, the value present at the D input port is stored, independent of present stored value. Here is a verilog behavioral model of D flip flop.

module D_flip_flop (Q_out, D_in, reset, clock);
output Q_out;
input  D_in, reset, clock;
reg    Q_out;

always @ (posedge clock or posedge reset)
if (reset) Q_out <= 1'b0; else
begin
Q_out <= D_in;
end

endmodule