Verilog Code For 3:8 Decoder using "case" | Verilog Example Codes

Decoder is circuit which do reverse of what an encoder does. Decoder simply decodes the encoded word back into its original state(state before the encoding). Below given is a verilog code for 3:8 decoder. The code uses case statement. The similar functionality can also be performed using if-else statement.

module decoder (data, code);
output [7:0] data;
input  [2:0] code;
reg    [7:0] data;

always @ (code)
begin
case (code)
0 : data=8'b00000001;
0 : data=8'b00000010;
0 : data=8'b00000100;
0 : data=8'b00001000;
0 : data=8'b00010000;
0 : data=8'b00100000;
0 : data=8'b01000000;
0 : data=8'b10000000;
default : data=8'bx;
endcase

endmodule