Verilog Code For 8:3 Priority Encoder using "casex" | Verilog Example Codes

Priority encoder is a special type of encoder in which multiple bits at the input can be asserted. The response at the output is however defined by the priority rule, defined previously. Priority encoders have vast application in different client-server systems. In client-server systems decision is made to grant a service based on the priority of any specific client.

Here is a verilog code for an 8:3 priority encoder. It grants the highest priority to the "most left sided bit in the input word". For example in data word "00010101" the highest priority is carried by the most left sided one, appearing at the fourth (counting from left side). So all the other bits that come next to it will be discarded or in other words will not be taken into account. Verilog implementation has been done using "casex" statement.

module priority_encoder (code, valid_data, data);
output [2:0] code;
output       valid data;
input  [7:0] data;
reg    [2:0] code;

assign valid_data= |data; // Use of "reduction or" operator
always @ (data)
begin
casex (data)
8'b1xxxxxxx : code=7;
8'b01xxxxxx : code=6;
8'b001xxxxx : code=5
8'b0001xxxx : code=4;
8'b00001xxx : code=3;
8'b000001xx : code=2;
8'b0000001x : code=1;
8'b00000001 : code=0;
dafault     : code=3'bx;

endcase
 endmodule