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Verilog Example Code for Full Adder | Verilog Codes

This is a verilog example code for full adder with zero delay or in other words no propagational delays have been taken into account. As we know a full adder is comprised of two half adders along with an OR gate. Thus code creates two instances where a call goes to module for half adder. Verilog allows nesting of modules in one another but, you cannot use them in recursive manner. The nodes inside the schematic other than input and output i.e., w1, w2, and w3 has been declared as wires. If not declared exclusively a variable is treated as a wire by default in verilog.

module Addfull_zero_delay (sum, C_out, a, b, C_in);

input a, b, C_in;
output C_out, sum;
wire w1, w2, w2;

halfadd_no_delay M1 (w1, w2, a, b);
halfadd_no_delay M2 (sum, C_out, C_in, w1);
or (C_out, w3, w2);

end module

// Moudule for half adder.

module halfadd_no_delay (Cout, sum, Ina, Inb)

input Ina, Inb;
output Cout, sum;

xor (sum, Ina, Inb);
and (Cout, Ina, Inb);