Verilog module Code For Universal Shift Register | Verilog Example Codes

A universal shift register is an important unit of digital machines that imploy a bit-slice architecture, with multiple identical slices of shift registers of same word length, chained together to form a more wider data path. It contains many explicit features which include parallel inputs, parallel outputs, synchronous reset, bidirectional serial input and bidirectional serial output.

The below presented verilog code for 4-bit universal shift register acts as a uni-directional shift register for serial-in and serial-out mode, by delaying the input signal upto 4 clock cycles.

The parallel-in, serial-out mode allows parallel-to-serial conversion. And serial-in, parallel-out mode converts the serial to parallel conversion of data-stream.

module Universal_shift_reg (data_out, msb_out, lsb_out, data_in,

msb_in, lasb_in, s1, s0, clk, rst);

output [3:0] data_out;            // Hold
output       msb_out, lsb_out;    // Serial shift from msb
input  [3:0] data_in;             // Serial shift from lsb
input        msb_in, lsb_in;      // Parallel load
input        s1, s0, clk, rst;
reg          data_out;

assign msb_out= data_out[3];
assign lsb_out= data-out[0];

always @ (posedge clk)
begin
 if (rst) data_out<=0;
 else case ({s1, s0})
 0 : data_out <= data_out;
 1 : data_out <= {msb_in, data_out[3:1]};
 2 : data_out <= {data_out[2:0], lsb_in};
 3 : data_out <= data_in;
 endcase
end
endmodule