This is a verilog example code of a half bit adder module. Half adder can add two bits and present the sum in the form of a sum bit and a carry bit. The code for half has been synthesized for zero delay so, delay has not taken into account. XOR and AND are two verilog primitives used.
module halfadd_no_delay (Cout, sum, Ina, Inb);input Ina, Inb;output Cout, sum;xor (sum, Ina, Inb);and (Cout, Ina, Inb);endmodule