Verilog module Code For Ring Counter | Verilog Example Codes

A ring counter asserts its one bit which circulates throughout the whole data word in a synchronous manner. Presented below is a verilog code for an eight bit ring counter. If an external synchronizing signal is provided i.e., a clock signal the asserted bit circulates throughout the register and then after completion of whole cycle, automatic restarting of counter occurs.

module ring_counter (count, enable, clock, reset);
output [7:0] count;
input        enable, reset, clock;
reg          count;

always @ (posedge reset or clock)
if(reset==1'b1) count <= 8'b0000_0001;
else if(enable==1'b1) count <= {count[6:0],count[7]};

endmodule