A negative number can be expressed in verilog by putting a
negative sign before that number. But it is invalid to put a sign after the
base format. See the example below for clarification.

**Example of a negative number in Verilog:**

z = - 14’ha345; // the value is stored as a 2’s complement

**Important Note:**The negation can be assigned only to a constant. The number is stored as a 2’s complement.

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