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Unsized Numbers in Verilog

Unsized numbers in Verilog are based on the default decimal base format. If base format  is not specified, the number becomes decimal based. If size is not specified, then that number takes a fixed amount of space (32 bits in most cases). The exact amount of space is however, simulator dependant as well as also depends upon architecture of machine.

Example of an unsized number:

z = 4567;     // z is a decimal number and takes 32 bits.

z = ‘hac;       // z is a 32 bit hexadecimal number .