Verilog Code For 32 bit Comparator | Verilog Example Codes

For implementation of complex circuits gate level modeling is hectic and error prone. As the size and complexity level grows the trend shifts from gate-level modeling to behavioral modeling of digital circuits. In behavioral models, all we have to do is to define the functionality (or behavior in other sense) of the circuit.

For example below given is an implementation of 32 bit comparator which otherwise if done using gate-level modeling is too much lengthy, error prone and hectic.

module comparator (a_gt_b, a_lt_b, a_eq_b, a, b);

parameter word_size=32;

input [word_size-1:0] a,b;

output a_gt_b, a_lt_b, a_eq_b;

assign a_gt_b = (a > b),

       a_lt_b = (a < b),

       a_eq_b = (a = b);

endmodule

The implementation has become more general by the use of "parameter". You can plug any value instead of 32 in "word_size" written after parameter. Hence parameter attribute has increased the reusability and generality of the module.