Verilog Code For Arithmetic Unit Using Function | Verilog Example Codes

Below given is a verilog module for an arithmetic unit. This units takes two words as an input and presents a sum along with a comparison, as an output. These two operations are performed using "function". The objective is to clear the concept of functions in verilog.

module arithmetic_unit (res_1, res_2, operand_1, operand_2);

output [4:0] res_1:

output [3:0] res_2;

input [3:0] operand_1, operand_2;

assign res_1 = sum_operands (operand_1, operand_2);

assign res_2 = largest_of_two (operand_1, operand_2);

function [4:0] sum_operands;

input [3:0] operand_1, operand_2;

sum_operands= operand_1 + operand_2;

endfunction

function [3:0] largest_of_two;

input operand_1, operand_2;

largest_of_two= (operand_1 > operand_2) ? operand_1 : operand_2;

endfunction

endmodule

The above code creates two functions to do the jobs. Remember, functions are are best used to improve the re usability of combinational logic. They cannot be used to replace event control (@) and delay control operators (#).