Verilog Code For 3:8 Decoder using "if-else" | Verilog Example Codes

Decoder is circuit which do reverse of what an encoder does. Decoder simply decodes the encoded word back into its original state(state before the encoding). Here is a verilog implementation of 3:8 decoder.

module decoder (data, code);
output [7:0] data;
input  [2:0] code;
reg    [7:0] data;

always @ (code)
begin
if(code==0) data=8'b00000001; else
if(code==1) data=8'b00000010; else
if(code==2) data=8'b00000100; else
if(code==3) data=8'b00001000; else
if(code==4) data=8'b00010000; else
if(code==5) data=8'b00100000; else
if(code==6) data=8'b01000000; else
if(code==7) data=8'b10000000; else
            data=8'bx;
end
endmodule