Verilog Comments

Comments helps to make the code statement  more understandable.  Like in C language, there are two ways to write comments in Verilog. Short comments that can be summed up in a single line can be given starting by (//). For longer comments one line might not be sufficient therefore multiple line comments can be given starting by (/*) and ending at (*/).  The star is present at the inner side.

Comment statements are ignored by simulator.

Important Note:  Multiple line comments written using (*/  …  */) can not be nested. See the example below for clarification.

Example of single line comment:

a = b || d;   // a is the result of ORing b and d.

Example of multiple line comment:

/* We are giving multiple

                        line comment here*/

Example of an invalid multiple  line comment:

/*        This is an example of /* multiple line */comment                  */