Verilog Code For JK Flip Flop | Verilog Example Codes

JK flip flop is an edge triggered storage element, which means that data is synchronized to an active edge of clock cycle. The active edge may be a positive or negative. The data stored on active edge is conditional, which means it is dependent on the data present at the J and K inputs, whenever clock makes a transition at an active edge.

module jk_flip_flop(J, K, clk, Q);
input J, K, clk;
output Q;
reg Q;
reg Qm;

always @(posedge clk)
if(J == 1 && K == 0)
Qm <= 1;else
if(J == 0 && K == 1)
Qm <= 0;else
if(J == 1 && K == 1)
Qm <= ~Qm;
Q <= Qm;

endmodule