Verilog Code For Transparent Latch | Verilog Example Codes

Synthesis of latch requires feedback when implemented using assign statement. Latch can be synthesized using conditional operator, using continuous assignment operator. Here is a simple verilog example code for latch synthesis in verilog. This is infact an important property which sometimes causes an unintentional synthesis of latches in hardware implementation.

Verilog Example Code for Latch

module latch (q_out, data_in, enable);

output q_out;

input  data_in, enable;

assign q_out = enable?data_in:q_out;

endmodule

The important point is that appearance of q_out in RHS and LHS implies a structural feedback in hardware.