Verilog Code For Multiplexer (MUX) | Verilog Example Codes

Here a simple verilog code for implementation of 2 by 32 multipler (Mux). The word size fed at the input is of size 32 bits, and has been declared as a 32 bit vector. But the code has been made portable by the use of "parameter". As we know "parameter" keyword is equivalent to #define in C language, so you can change the variable word_size size according to your desired value. The implementation has been done using "assign" keyword. Assign keyword can model both combinational and level sensitive logic. Assign keyword will cause the mux_out (output of mux) to respond according to the change in the input.

Verilog Code for Multiplexer (Mux)

module Mux_2_32 (mux-out, data_1, data_0, select);

parameter word_size = 32;

output [word_size - 1: 0] mux_out;

input  [word_size - 1: 0] data_1, data_0;

input  select;

assign mux_out = select?data_1:data0;

endmodule