Verilog language Rules

Verilog is a case sensitive language. So a variable named “Z” and “z” are treated as two different variables. The keywords are always in lower case letters. For example, it is invalid to write “Module” instead of “module”. The other language rules are described below:

• Ø  White space in Verilog

• Ø  Comments in Verilog

• Ø  Verilog number system
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