Verilog Code For 4 Bit Serial Shift Register | Verilog Example Codes

Here is verilog code for implementation of a 4 bit serial shift register. See that the implementation has been done using non-blocking assignment operator (<=). If this was done with the help of blocking assignment operator (=), the case would be different. the similar code written using blocking statements would synthesize to a different circuit during synthesis.

This behavior is due to the fact that blocking assignment operators execute one-by-one while, non-blocking assignment operators execute concurrently during simulation.

module serial_shift (a, e, clock, reset);

output a;

input clock, reset;

input e;

reg a, b, c, d;

always @ (posedge clock or posedge reset)

 if (reset) begin a<=0, b<=0, c<=0, d<=0; end

 else begin

a<=b;

b<=c;

c<=d

d<=e;

 end

end

endmodule